
_main:
	LDI        27, 255
	OUT        93, 27
	LDI        27, 0
	OUT        94, 27
	IN         28, 93
	IN         29, 94
	SBIW       28, 13
	OUT        93, 28
	OUT        94, 29
	ADIW       28, 1
;UART_Incoming.mpas,12 :: 		begin
;UART_Incoming.mpas,13 :: 		UART1_Init(9600);                         // Initialize UART module at 9600 bps
	LDI        27, 51
	OUT        41, 27
	LDI        27, 0
	OUT        64, 27
	CALL       _UART1_Init+0
;UART_Incoming.mpas,14 :: 		Delay_ms(100);                            // Wait for UART module to stabilize
	LDI        18, 5
	LDI        17, 15
	LDI        16, 242
	DEC        16
	BRNE       $-1
	DEC        17
	BRNE       $-3
	DEC        18
	BRNE       $-5
;UART_Incoming.mpas,15 :: 		UART1_Write_Text('UART_READY:');
	MOVW       30, 28
	LDI        27, 85
	ST         Z+, 27
	LDI        27, 65
	ST         Z+, 27
	LDI        27, 82
	ST         Z+, 27
	LDI        27, 84
	ST         Z+, 27
	LDI        27, 95
	ST         Z+, 27
	LDI        27, 82
	ST         Z+, 27
	LDI        27, 69
	ST         Z+, 27
	LDI        27, 65
	ST         Z+, 27
	LDI        27, 68
	ST         Z+, 27
	LDI        27, 89
	ST         Z+, 27
	LDI        27, 58
	ST         Z+, 27
	LDI        27, 0
	ST         Z+, 27
	MOVW       16, 28
	PUSH       17
	PUSH       16
	CALL       _UART1_Write_Text+0
	IN         26, 93
	IN         27, 94
	ADIW       26, 2
	OUT        93, 26
	OUT        94, 27
;UART_Incoming.mpas,16 :: 		delay_ms(10);
	LDI        17, 104
	LDI        16, 229
	DEC        16
	BRNE       $-1
	DEC        17
	BRNE       $-3
;UART_Incoming.mpas,17 :: 		ddrd:=0xFF;
	LDI        27, 255
	OUT        49, 27
;UART_Incoming.mpas,19 :: 		while TRUE do    // loop cycle
L__main2:
;UART_Incoming.mpas,21 :: 		if (UART1_Data_Ready() <> 0) then     // If data is received,
	CALL       _UART1_Data_Ready+0
	CPI        16, 0
	BRNE       L__main19
	JMP        L__main7
L__main19:
;UART_Incoming.mpas,23 :: 		uart_rd := UART1_Read();          //   read the received data,
	CALL       _UART1_Read+0
	STS        _uart_rd+0, 16
;UART_Incoming.mpas,24 :: 		if (uart_rd = 'P') then
	CPI        16, 80
	BREQ       L__main20
	JMP        L__main10
L__main20:
;UART_Incoming.mpas,26 :: 		UART1_WRITE_TEXT('IM READY!');
	MOVW       30, 28
	LDI        27, 73
	ST         Z+, 27
	LDI        27, 77
	ST         Z+, 27
	LDI        27, 32
	ST         Z+, 27
	LDI        27, 82
	ST         Z+, 27
	LDI        27, 69
	ST         Z+, 27
	LDI        27, 65
	ST         Z+, 27
	LDI        27, 68
	ST         Z+, 27
	LDI        27, 89
	ST         Z+, 27
	LDI        27, 33
	ST         Z+, 27
	LDI        27, 0
	ST         Z+, 27
	MOVW       16, 28
	PUSH       17
	PUSH       16
	CALL       _UART1_Write_Text+0
	IN         26, 93
	IN         27, 94
	ADIW       26, 2
	OUT        93, 26
	OUT        94, 27
;UART_Incoming.mpas,27 :: 		UART1_WRITE(0xA);
	LDI        27, 10
	PUSH       27
	CALL       _UART1_Write+0
	IN         26, 93
	IN         27, 94
	ADIW       26, 1
	OUT        93, 26
	OUT        94, 27
;UART_Incoming.mpas,28 :: 		UART1_WRITE(0xD);
	LDI        27, 13
	PUSH       27
	CALL       _UART1_Write+0
	IN         26, 93
	IN         27, 94
	ADIW       26, 1
	OUT        93, 26
	OUT        94, 27
;UART_Incoming.mpas,29 :: 		END;
L__main10:
;UART_Incoming.mpas,30 :: 		if (uart_rd = '1') then
	LDS        16, _uart_rd+0
	CPI        16, 49
	BREQ       L__main21
	JMP        L__main13
L__main21:
;UART_Incoming.mpas,32 :: 		UART1_WRITE_TEXT('relay is ON');
	MOVW       30, 28
	LDI        27, 114
	ST         Z+, 27
	LDI        27, 101
	ST         Z+, 27
	LDI        27, 108
	ST         Z+, 27
	LDI        27, 97
	ST         Z+, 27
	LDI        27, 121
	ST         Z+, 27
	LDI        27, 32
	ST         Z+, 27
	LDI        27, 105
	ST         Z+, 27
	LDI        27, 115
	ST         Z+, 27
	LDI        27, 32
	ST         Z+, 27
	LDI        27, 79
	ST         Z+, 27
	LDI        27, 78
	ST         Z+, 27
	LDI        27, 0
	ST         Z+, 27
	MOVW       16, 28
	PUSH       17
	PUSH       16
	CALL       _UART1_Write_Text+0
	IN         26, 93
	IN         27, 94
	ADIW       26, 2
	OUT        93, 26
	OUT        94, 27
;UART_Incoming.mpas,33 :: 		UART1_WRITE(0xA);
	LDI        27, 10
	PUSH       27
	CALL       _UART1_Write+0
	IN         26, 93
	IN         27, 94
	ADIW       26, 1
	OUT        93, 26
	OUT        94, 27
;UART_Incoming.mpas,34 :: 		UART1_WRITE(0xD);
	LDI        27, 13
	PUSH       27
	CALL       _UART1_Write+0
	IN         26, 93
	IN         27, 94
	ADIW       26, 1
	OUT        93, 26
	OUT        94, 27
;UART_Incoming.mpas,35 :: 		portd.5:=1;
	SBI        50, 5
;UART_Incoming.mpas,36 :: 		portd.6:=1;
	SBI        50, 6
;UART_Incoming.mpas,37 :: 		END;
L__main13:
;UART_Incoming.mpas,39 :: 		if (uart_rd = '0') then
	LDS        16, _uart_rd+0
	CPI        16, 48
	BREQ       L__main22
	JMP        L__main16
L__main22:
;UART_Incoming.mpas,41 :: 		UART1_WRITE_TEXT('relay is OFF');
	MOVW       30, 28
	LDI        27, 114
	ST         Z+, 27
	LDI        27, 101
	ST         Z+, 27
	LDI        27, 108
	ST         Z+, 27
	LDI        27, 97
	ST         Z+, 27
	LDI        27, 121
	ST         Z+, 27
	LDI        27, 32
	ST         Z+, 27
	LDI        27, 105
	ST         Z+, 27
	LDI        27, 115
	ST         Z+, 27
	LDI        27, 32
	ST         Z+, 27
	LDI        27, 79
	ST         Z+, 27
	LDI        27, 70
	ST         Z+, 27
	LDI        27, 70
	ST         Z+, 27
	LDI        27, 0
	ST         Z+, 27
	MOVW       16, 28
	PUSH       17
	PUSH       16
	CALL       _UART1_Write_Text+0
	IN         26, 93
	IN         27, 94
	ADIW       26, 2
	OUT        93, 26
	OUT        94, 27
;UART_Incoming.mpas,42 :: 		UART1_WRITE(0xA);
	LDI        27, 10
	PUSH       27
	CALL       _UART1_Write+0
	IN         26, 93
	IN         27, 94
	ADIW       26, 1
	OUT        93, 26
	OUT        94, 27
;UART_Incoming.mpas,43 :: 		UART1_WRITE(0xD);
	LDI        27, 13
	PUSH       27
	CALL       _UART1_Write+0
	IN         26, 93
	IN         27, 94
	ADIW       26, 1
	OUT        93, 26
	OUT        94, 27
;UART_Incoming.mpas,44 :: 		portd.5:=0;
	CBI        50, 5
;UART_Incoming.mpas,45 :: 		portd.6:=0;
	CBI        50, 6
;UART_Incoming.mpas,46 :: 		END;
L__main16:
;UART_Incoming.mpas,47 :: 		end;
L__main7:
;UART_Incoming.mpas,48 :: 		END;
	JMP        L__main2
;UART_Incoming.mpas,50 :: 		end.
L_end_main:
	JMP        L_end_main
; end of _main
